Overview: Individually developed in schematics, test-benches, and layouts of a Differential Amplifier with Code-Controlled Bus Connection created with the TSMC 65nm foundry-based PDK. The system features a code-checker that utilizes CMOS-logic to determine if the correct code is inputted, followed by multiple transmission gates to trigger the differential amplifier. The code checker is created utilizing NAND gates, and utilizing a power-grid layout technique. The amplifier utilizes a current mirror with PMOS active loads to achieve a gain of over 25dB at 1MHz.
Note: Layout images, component values, and simulation results are not included in portfolio due to agreements with TSMC regarding their PDKs.
Full System
Amplifier: Utilized current mirror differential amplifier with active load. Obtained a 28.75 dB gain at 1 MHz, with a peak to peak output swing of 513.2 mV, and a power consumption of 65.2uW. Design tradeoffs included sizing of transistor, usage of fingers, and selection of topology, to maximize gain while minimizing power consumption. Considerations were also made with regard to layout, requiring compactness within a limited space.
Code Checker: Creating a code checker to ensure my amplifier was only turned on with the right code inputted to the IC, I was required to use CMOS digital logic, while also minimizing space usage in layout, and minimizing propagation delay. I decided to utilize NAND gates, as they are universal logic gates that are functionally complete, allowing for simple use throughout the code checker. Mosfet sizing considerations included minimizing both rise and fall time, as well as overall propagation delay. In simulations, the gate had a rise time of 17.85ps, a fall time of 18.3ps, and a propagation delay of 13.97ps.
After designing the NAND gate, I created the truth table required for my code checker and my code given (0111), and wired up my NAND gates such that they would only output high when the correct code was input. The full code checker had a propagation delay of 262.2ps.
